Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum feature size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional integrated circuits (3DICs) were thus formed, wherein at least two dies may be stacked, with through-substrate vias (TSVs) formed in one of the dies to connect the other die to a package substrate. These 3DICs generally incurred problems. For example, the connectivity of a die, such as a top die, to another component required a dependency on the design of other dies intervening between the die and the other component. Also, the stack height is generally limited by a yield requirement. Typically, as the stack height increases by the addition of dies, the yield decreases because a fault in any die would render the entire structure faulty, and an increased number of dies increases the probability that any one of the dies will fail. Further, a bottom die generally is a thermal and current “hot spot” in the stack because during the normal operation of the dies, a relatively large current flowing through the bottom die to top dies from a power source, and because there is a large distance to a package heat sink above the topmost die. Next, these structures may have a footprint that is too small to contain all Controlled Collapse Chip Connection (“C4”) bumps or solder balls that are required for various applications.
Also, the semiconductor industry has formed what are known as two and one half-dimensional integrated circuits (2.5DICs), wherein at least two dies may be connected to an interposer, which is in turn connected to a package substrate. These structures may be limited by an interposer size, which is limited by a reticle, a yield, and a package requirement. Also, the footprint may be too big for some products. Further, wire lengths and power consumption are not reduced compared to monolithic devices. A hot spot may occur in the center of the interposer due to global routing of electrical signals.